Extending the award-winning MIPS Aptiv generation of CPU cores

Paul Evans, senior business development manager for Imagination, recently gave an exciting keynote at the Imagination Summit in Asia titled ‘MIPS CPU Processor Solutions: A Roadmap to High Performance and Low Power’. During this exciting and well-attended presentation, he talked about the latest developments within our MIPS Aptiv generation of CPU IP and introduced MIPS Series5 ‘Warrior’ – a forthcoming generation of processors based on the MIPS32 and MIPS64 architectures.

You can find out more about the ‘Warrior’ cores and get a preview of their features here; right now I am going to offer you an overview of the latest news regarding our MIPS Aptiv generation of cores.

Let’s rewind a bit for those of you who are new to our MIPS Aptiv CPUs. It was only a year ago that the Aptiv generation of processors was launched to positive reviews and general acclaim from industry partners and analysts, from Anandtech and Engadget to EE Times and the Linley Group. Right after its announcement, the MIPS Aptiv family received the ‘Best processor IP 2012’ award from the Linley Group and the ‘Top Innovative Product of 2012’ distinction from Embedded Computing Design and was included on the EDN Hot 100 Product list.

Each Aptiv CPU core is based on the same underlying MIPS32 architecture and has particular features focused on delivering peak performance in key applications, while reducing area and power consumption.

New single-core interAptiv CPU joins dual- and quad-core configurations

The interAptiv family is the 3rd generation of MIPS-based IP cores to leverage multithreading, providing better overall throughput, QoS and power/performance efficiency in applications such as networking, storage, and image and audio processing.

The single-core interAptiv has been designed to provide an area-optimized and power efficient solution which is ideal for customers wishing to upgrade from our single-core MIPS classic cores. interAptiv suits an array of cost-effective use cases such as baseband modems, audio processing/codecs, automotive, storage and other high-reliability applications, as it supports a variety of real time operating systems.

MIPS interAptiv single core block diagram - MIPS Aptiv generationSingle-core MIPS interAptiv block diagram

With the single-core interAptiv, we’re bringing the features of the interAptiv multicore family down to a product that serves as the next generation and easy migration path for silicon vendors.

The single core, non-coherent version of interAptiv (announced recently during the Imagination Summit) extends available memory space with Enhanced Virtual Address (EVA) technology, supports ECC (Error Code Correction) for safety-critical applications and includes a multi-threaded FPU (Floating Point Unit), providing an enhanced architectural design compared to our MIPS32 classic cores. Dynamic power consumption was reduced from that of its predecessor, the MIPS 34K. It also updates the DSP capabilities by incorporating DSP ASE rev2, aligning it with existing Aptiv products.

The interAptiv multi-threaded CPU has the same advantages in terms of programming concepts as a traditional multicore solution, but reduces area significantly. For example, when executing advanced software stacks such as an LTE baseband implementation within an SMP operating system environment running on power-efficient MIPS multi-threaded cores, our customers are able to achieve performance increase of 30-45% over a single-threaded platform.

interAptiv provides an optimized solution that is highly configurable, as it doesn’t overload on unnecessary power-hungry features, and avoids attaching processing elements that are of no use in the typically closed systems where a CPU like interAptiv will be used.

How about a high performance multicore CPU for mobile?

proAptiv is the star of high performance 32-bit processors, with a triple-dispatch superscalar, Out of Order (OoO) architecture that has best-in-class branch prediction, delivering competitive top-line performance for today’s complex software workloads. It features our EVA technology, a high-speed FPU, and high-performance cache memories.

proAptiv is designed for peak performance efficiency when running 3rd party applications, playing demanding games under Android or browsing the web. It can scale from one to six different cores, enabling ‘4+1’ hardware configurations which offer a simpler hardware approach to lower power designs. With this type of multiprocessing, software management of both performance and power becomes more natural when varying frequency.

MIPS proAptiv block diagram  - MIPS Aptiv generationMIPS proAptiv block diagram

proAptiv delivers a highly balanced design; instruction bonding and a streamlined pipeline provide the required performance for handling large, highly complex, virtual machine workloads while keeping power consumption in check. This enables proAptiv to achieve superior performance per mm2 while being 40% smaller in area compared to competing CPU IP designs.

For example, the latest CoreMark benchmarking numbers put proAptiv significantly ahead of competing solutions. CoreMark is an industry-recognized benchmark that provides a single number score for quick comparison of processor and microcontroller core functionality.

proAptiv CoreMark results  - MIPS Aptiv generationLatest CoreMark benchmark results for a single-core proAptiv CPU

proAptiv is a very flexible CPU that includes DSP extensions for common audio and image processing tasks; it can be implemented in coherent multicore systems or as a single core solution that still includes hardware acceleration of coherent I/O transactions and an L2 cache controller.

Taking on the Internet of Things with microAptiv

microAptiv is the crown jewel of microcontroller cores:  in the same size and power consumption of competing solutions, it uniquely features the capability to be configured with an MMU (Memory Management Unit) or an MPU (Memory Protection Unit), allowing system designers to choose whether they include support for Linux.

This is a very important aspect for platforms designed for the Internet of Things (IoT) and machine-to-machine (M2M) communications, where ultra-low power consumption and configurability are key factors. Connected IoT and M2M devices must also perform smart tasks associated with real time processing.

microAptiv provides the ideal answer for all of the above; it is designed to suit a range of embedded applications and can scale in frequency from tens to hundreds of MHz. You can find microAptiv at the heart of embedded controllers for the analogue world, industrial applications, home appliances, communications, and even down into mobile. The newest member of the microAptiv family now incorporates an optional hardware floating point unit for applications including electric metering and motor control.

MIPS Aptiv microAptiv UC block diagramMIPS microAptiv microcontroller core with an MPU and FPU

MIPS Aptiv microAptiv UP block diagramMIPS microAptiv microprocessor core with an MMU

microAptiv has a high performance and efficient pipeline, leveraging the inherent advantages of the MIPS architecture to provide an optimal balance of speed, area and power usability. It features standard memory and I/O interfaces that enable easy connection to a wide range of peripherals while delivering the highest DMIPS/MHz and CoreMark/MHz score in its class.

microAptiv performance - MIPS Aptiv generation

It supports our microMIPS ISA, which achieves important code size reductions that keep memory costs down. This is a very important area in embedded applications. If you look at a typical embedded system, an MCU core such as microAptiv only takes around 5% of the total area, while memory can take up as much as 40%. By enabling code compression through microMIPS, we are helping our partners like Microchip Technology achieve performance efficiency and reduced system area, while keeping memory related-costs down.

Building on the strength of the MIPS Aptiv generation

All these features, together with a series of micro-architectural improvements and design innovations, give the proAptiv, interAptiv and microAptiv CPU IP families the upper hand in the battle for supremacy in the microprocessor space.

Moving forward, we are committed to growing the available CPU IP portfolio and provide our partners with the latest features in the dynamic world of CPU IP. The upcoming MIPS Series5 ‘Warrior’ generation of cores will feature 32-bit and 64-bit variants, and implement a series of compelling architectural features. If you weren’t able to attend our Imagination Summit in China or Taiwan, make sure you read our article about the MIPS Series5 ‘Warrior’ CPUs for some ‘behind the scenes’ details on how these cores will offer superior features, leading performance and advanced functionality.

What do you think about our existing Aptiv cores? Are you excited about the MIPS Series5 ‘Warrior’ CPUs? Leave us a comment in the box below and follow us on Twitter (@ImaginationPR and @MIPSGuru) for the latest news and announcements from Imagination, our partners and licensees.

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