Cavium introduces the MIPS64-based OCTEON III CPU family for ultra-high performance networking

Cavium has been a leading provider of highly integrated semiconductor products for networking, communications and cloud infrastructure for years, but things are about to get even more interesting thanks to the recent launch of OCTEON III, a new family of processors that is poised to make an impact in the enterprise systems market.

Its brand new members of the ultra-high performance OCTEON III family of networking multicore processors are set to incorporate the latest features of the MIPS64 architecture (MIPSr5), making it one of the first 64-bit CPU RISC processors on the market to include full hardware virtualization.

An overview of Cavium’s OCTEON MIPS64-based processors

Cavium continues to leverage our proven MIPS64 architecture for OCTEON, a scalable processor line enabling a single high performance solution from entry-level to high-end markets. MIPS64-based OCTEON multicore processors provide a viable alternative for intelligent networking that is built on the low power principles of Imagination’s MIPS64 architecture.

OCTEON OCTEON II OCTEON III

Cavium’s MIPS64-based OCTEON multicore processor family

OCTEON CPUs are available in multiple versions to address market specific requirements, including Network Services Processors (NSP), Application Acceleration Processors (AAP), Storage Services Processors (SSP), Secure Communication Processors (SCP) and Communication Processors (CP). Their compute performance (100Mbps to 100Gbps) has been tuned to meet and exceed the requirements of modern applications.

Thanks to the popular, industry-standard MIPS64 ISA, Cavium has designed OCTEON to be a software-compatible processor family that can scale from one to forty-eight cnMIPS cores on a single chip, integrating next-generation networking I/Os and peripherals on the same die. The OCTEON product family is also fully supported by a wide range of toolchains and all major operating systems.

Introducing the fully featured MIPS64-based Cavium OCTEON III family

The latest MIPS64 architecture enhancements from Imagination combined with Cavium’s in-house design expertise have led to the creation of OCTEON III, one of the most advanced 64-bit processor families available on the market today. It provides among the highest compute power of any standards-based communications processors, with 120GHz of 64-bit compute processing per chip.

Another major benefit of OCTEON III lies in its ability to deliver a high level of performance and features at a very attractive price for network hardware and storage applications.

Cavium OCTEON III MIPS64-based family block diagram

The Cavium OCTEON III MIPS64-based processor

By moving to the 28nm process node and creating an innovative power saving technology, the Cavium OCTEON III family offers up to 4x performance over MIPS64-based OCTEON II processors, all in a similar power envelope.

Fully featured, high performance, low power 64-bit computing with MIPS64

Based on a heritage built and continuously innovated over more than two decades, the MIPS64 architecture relies on a fixed-length, regularly encoded instruction set.

MIPS64 is one of the most reliable 64-bit RISC architectures in use today, adopting the standard load/store RISC data model. It enables a very efficient execution of high-level languages (arithmetic and logic operations utilize a three-operand format), allowing compilers to optimize complex expression formulation.

Over the years, the 64-bit MIPS architecture has been successfully used by companies such as DeskStation Technology (Windows NT personal computers and DeskStation Tyne workstation), NEC Corporation (RISCstation workstations, RISCserver servers, and Cenju-3 supercomputer), NeTPower (Windows NT workstations and servers), Pyramid Technology (Nile Series servers), Siemens (RM-series UNIX servers and SR2000 mainframe), Silicon Graphics (Onyx, Indigo, Indigo2, and Indy workstations and Challenge server) or The Institute of Computing Technology of the Chinese Academy of Sciences (Loongson 2 and 3 processors for a range of applications including supercomputers). Other licensees over the years included AMD, Infineon, Renesas, Sony, STMicroelectronics and numerous others. You can also find the MIPS64 architecture at the heart of Broadcom’s most recent ultra-high performance single core and multicore, multithreaded CPUs for data centers, carrier providers, home and enterprise networks.

MIPS64-r4000lrgFull die shot of Toshiba’s R4000 microprocessor, the first 64-bit MIPS CPU launched in 1991*

A great advantage of MIPS64 is its ability to provide a 32-bit mode where applications developed for the MIPS32 architecture are fully software compatible and can run without changes. By providing backward compatibility, standardizing privileged mode, and memory management, the MIPS64 architecture enables efficient code reuse for real-time operating systems and applications across all MIPS32 and MIPS64-based processor families. Furthermore, all MIPS64 and MIPS32-based processors that feature a TLB (Translation Lookaside Buffer) meet the memory management requirements of Linux, Android, Windows CE and other popular operating systems.

But perhaps best of all, when adopting MIPS, the same toolchain can be used on the whole range of our CPU IP, from the Aptiv family (microAptiv UP, interAptiv, proAptiv) all the way up to the 64-bit powerhouses from Cavium or Broadcom, which is a major benefit when creating common software development kits.

By licensing our MIPS64 IP, companies like Cavium are able to stay ahead of the current 64-bit RISC CPU pack with a reliable, proven 64-bit architecture that delivers full hardware virtualization support and optimized software stacks, two vital building blocks that enable success in the enterprise networking market.

To stay up to date with the exciting developments of our MIPS architecture and roadmap, make sure you follow us on Twitter (@ImaginationPR and @MIPSGuru) and keep coming back to our blog.

 

* Image courtesy of Molecular Expressions, all rights reserved.

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